The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising
edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing
control bit, TMR1ON (T1CON<0>). Timer1 also has an internal “Reset input”. This Reset
can be generated by either of the two CCP modules.When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as ‘0’. Additional information on timer modules is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023).
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