TIMER0 CAPTURE INTERRUPT OF LPC2129/38(ARM7)

#include<lpc21xx.h>

void delay();
__irq void capint();
int main()
{
PINSEL0=0X00000020;
IO1DIR=0XFFFFFFFF;
T0TCR=1;
 T0CCR=0X05;
T0TC=0X00000000;

VICVectCntl0=0x24;
VICIntEnable=0x00000010;
VICVectAddr0=(unsigned)capint;
while(1);

}

__irq void capint()
{
IO1SET=0XFFFFFFFF;
delay();
IO1CLR=0XFFFFFFFF;
delay();
T0IR=0X10;
VICVectAddr=0;
}

void delay()
{
int i;
for(i=0;i<10000000;i++);
}

UART INTERRUPT OF LPC2129/38(ARM7)

#include<lpc21xx.h>

__irq void uartint(void);
void delay(void);
int main()
{IO1DIR=0XFFFFFFFF;
PINSEL0=0X00000004;
U0LCR=0X83;
U0DLM=0X00;
U0DLL=0X51;
U0LCR=0X03;
U0IER=0X01;

VICVectAddr0=(unsigned)uartint;
 VICIntSelect=0x00000000;
VICIntEnable=0x00000040;
VICVectCntl0=0x00000026;

  while(1)
  {
   delay();
  }
  }
 __irq void uartint()
 {
   U0IIR=0X04;
  IO1SET=0XFFFFFFFF;
  delay();
  IO1CLR=0XFFFFFFFF;
  delay();
  //U0IER=0X01;
  
   VICVectAddr=0;
  }
  void delay()
  {
  int i;
  for(i=0;i<1000000;i++);
  }

EXTERNAL INTERRUPT PROGRAMMING OF LPC2129/38(ARM7)

#include<lpc21xx.h>
void delay();
__irq void extint();
int main()
{
 IO0DIR=0;
IO1DIR=0XFFFFFFFF;
PINSEL0=0X0000000C;
//PINSEL1=0X00000001;
//EXTINT=0X0;
//EXTMODE=0X00;
//EXTPOLAR=0X01;
VICVectCntl0=0x0000002E;
  VICVectAddr0=(unsigned)extint;
 //VICIntSelect=0x00000000;
VICIntEnable=0x00004000;
EXTINT=0X01;

while(1)
{ //EXTINT=0X01;
delay();
}

}
void extint()__irq
{

IO1CLR=0XFFFFFFFF;
delay();
IO1SET=0XFFFFFFFF;
delay();
  VICVectAddr=0;


}
void delay()
{
int i,j;
//for(j=0;j<k;j++)
for(i=0;i<10000;i++);
}

LPC2129/38(ARM7) INTERRUPT PROGRAMMING

VECTORED INTERRUPT CONTROLLER (VIC)

FEATURES
• ARM PrimeCell™ Vectored Interrupt Controller
• 32 interrupt request inputs
• 16 vectored IRQ interrupts
• 16 priority levels dynamically assigned to interrupt requests
• Software interrupt generation
DESCRIPTION
The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and programmably assigns them into 3 categories, FIQ,vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request
is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority, but ony 16 of the 32 requests can be assigned to this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. All registers in the VIC are word registers. Byte and half word reads and write are not supported. Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell™ Vectored Interrupt Controller
(PL190) documentation.

INTERRUPT SOURCES

TIMER0 OVERFLOW INTERRUPT OF ATMEGA32

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
ISR(TIMER0_OVF_vect)
{
PORTA=0Xff;
_delay_ms(10000);
PORTA=0X00;
_delay_ms(1000);
TIFR|=0x01;

}
int main(void)
{
DDRA=0XFF;
SREG=0X80;
TIMSK=0x01;
TCCR0=0X05;
TCNT0=0X00;
//OCR0=0xff;
    while(1);

}

TIMER2 COMPARE INTERRUPT OF ATMEGA32

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
ISR(TIMER2_COMP_vect){

       TIFR|=0X80;

PORTA=0XFF;

_delay_ms(500);

PORTA=0X00;

}
int main(void)
{
DDRA=0XFF;
SREG=0X80;
TIMSK=0X80;
TCCR2=0X07;
TCNT2=0X00;
    while(1);
    {
     _delay_ms(500);
    }
}

TIMER1 COMPARE INTERRUPT OF ATMEGA32

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
ISR(TIMER1_COMPA_vect){
PORTA=0xff;
_delay_ms(500);
PORTA=0x00;
    //TIFR|=0X10;
}
ISR(TIMER1_COMPB_vect){
PORTB=0XFF;
_delay_ms(500);
PORTB=0X00;
TIFR|=0X08;
}
int main(void)
{
DDRA=0XFF;
DDRB=0XFF;
SREG=0X80;
TIMSK=0X18;
TCCR1A=0X00;
TCCR1B=0X05;
TCNT1H=0X00;
TCNT1L=0X00;
OCR1AH=0XB0;
OCR1AL=0X00;
OCR1BH=0XF0;
OCR1BL=0X00;
    while(1);
    }

TIMER1 OVERFLOW VECTOR INTERRUPT (ATMEGA32)

Blink a port when an overflow occurs

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>

ISR(TIMER1_OVF_vect){

TCNT1H=0XA0;
TCNT1L=0X00;
PORTA=0XFF;
_delay_ms(1000);
PORTA=0X00;
TIFR|=0x04;
}
int main(void)
{
    DDRA=0XFF;
SREG=0X80;
//TCCR1A=0x00;
TCCR1B=0X05;
TIMSK=0X04;

TCNT1H=0XA0;
TCNT1L=0X00;

while(1);

}

External Interrupt programming(INT0) of ATMEGA32

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>

ISR(INT0_vect){
PORTA=0XFF;
_delay_ms(500);
PORTA=0X00;
_delay_ms(500);
}

int main(void)
{
//DDRD=0x00;
DDRA=0XFF;

MCUCR=0X02;
//MCUCSR=0X00;

GICR=0X40;

SREG=0X80;

TCCR0=0x05;

while(1);
}    

ATMEGA32 Interrupts

Reset and Interrupt Vectors

USART INTERRUPT PROGRAMMING OF PIC16F877A(RECEIVER INTERRUPT)

#include<pic.h>
void transmit();
void main()
{
TXSTA=0X24;
RCSTA=0X90;
SPBRG=0X19;
TRISB=0X80;
RCIE=1;
GIE=1;
PEIE=1;
}
void interrupt isr()
{
char a;
if(RCIF==1)
{
a=RCREG;
transmit();
RCIF=0;
}

}
void transmit()
{
TXREG='t';
while(TXIF==0);
TXIF=0;
}

TIMER INTERRUPT PROGRAMMING OF PIC16F877A

Blink a port in every 1sec

#include<pic.h>
void delay(int);
int m=0;
void main()
{
TRISC=0X00;
OPTION=0X07;
TMR0=0X00;
GIE=1;
PEIE=1;
TMR0IE=1;
while(1);
}
void interrupt isr()
{
if(TMR0IF==1)
{
m++;
while(m<30)
{
PORTC=0XFF;
delay(10);
PORTC=0X00;
delay(10);
}
}
delay(100);
TMR0IF=0;
}
void delay(int k)
{
int j,i;
for(i=0;i<k;i++)
for(j=0;j<1000;j++);
}

EXTERNAL INTERRUPT PROGRAMMING OF PIC16F877A

Blinking of a port when a switch is pressed (switch is connected to the external interrupt pin)

#include<pic.h>
void delay(int);
void main()
{
int i;
TRISB=0XFF;
TRISC=0X00;
GIE=1;
PEIE=1;
INTE=1;
while(1)
{
PORTC=0X80;
for(i=0;i<8;i++)
{
PORTC=PORTC>>1;
}
}
}
void interrupt isr()
{
if(INTF==1)
{
PORTC=0XFF;
delay(25);
PORTC=0X00;
delay(25);
}
INTF=0;
}
void delay(int k)
{
int i,j;
for(i=0;i<k;i++)
for(j=0;j<1000;j++);

}

PIC16F877A Interrupt Programming:REGISTERS

Port blinking using Timer0 External Match(ARM7(LPC2129/38))

#include<lpc21xx.h>
int main()
{
IO1DIR=0XFFFFFFFF;
PINSEL1=0X00003000;
T0TCR=1;
T0TC=0;
T0MCR=0X003;
T0MR0=0X00FFFFFF;
T0EMR=0X031;
while(1)
{
while((T0IR&0X01)==0);
IO1SET=0XFFFFFFFF;
T0IR=0XFF;
while((T0IR&0X01)==0);
IO1CLR=0XFFFFFFFF;
T0IR=0XFF;
}
}

Port blinking using Timer0 Capture control(ARM7(LPC2129/38)

#include<lpc21xx.h>
int main()
{
IO1DIR=0XFFFFFFFF;
PINSEL1=0X00802000;
T0TCR=1;
T0TC=0;
T0MCR=0X001;
T0MR0=0X00FFFFFF;
T0CCR=0X009;
while(1)
{
while((T0IR&0X01)==0);
IO1SET=0XFFFFFFFF;
T0IR=0XFF;
while((T0IR&0X01)==0);
IO1CLR=0XFFFFFFFF;
T0IR=0XFF;
}
}

PORT Blinking using TIMER0 MATCH (LPC2129/38)

 #include<lpc21xx.h>

 int main()

 {

 IO1DIR=0XFFFFFFFF;

 T0TCR=1;

 T0MCR=0x019;

 T0TC=0X00000000;

 T0MR0=0X000F0000;

 T0MR1=0X00FF0000;

 while(1)

 {

 T0IR=0XFF;

 while((T0IR&0X01)==0);

 IO1SET=0XFFFFFFFF;

 while((T0IR&0X02)==0);

 IO1CLR=0XFFFFFFFF;

  }

  }

ARM7(LPC2129/38) : TIMER0 AND TIMER1

Timer0 and Timer1 are functionally identical except for the peripheral base address.

FEATURES
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A
capture event may also optionally generate an interrupt.
• Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match.
- Stop timer on match with optional interrupt generation.
- Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following capabilities:
- Set low on match.
- Set high on match.
- Toggle on match.
- Do nothing on match.

APPLICATIONS
• Interval Timer for counting internal events.
• Pulse Width Demodulator via Capture inputs.
• Free running timer.

REGISTER DESCRIPTION

PORT Blinking using TIMER2

#include <avr/io.h>
#include<util/delay.h>
int main(void)
{

 int i;
 DDRA=0xff;
PORTA=0x00;
TCCR2=0x07;

 while(1)
 {  
for(i=0;i<7;i++)
{
   TCNT2=0xff;
while((TIFR&0x40)==0);
TIFR|=0X40;
}
PORTA=PORTA^0XFF;
    }
}

Timer/Counter2 of ATMEGA32

Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The

main features are:

• Single Compare unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

• Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt

request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and

TIMSK are not shown in the figure since these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive

when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clkT2).

The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the waveform generator to generate

a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare

Unit” on page 116. for details. The compare match event will also set the Compare Flag (OCF2)

which can be used to generate an output compare interrupt request.

Blinking of LED using TIMER1

#include <avr/io.h>

int main(void)
{DDRA=0XFF;
//TCCR1A=0x00;
TCCR1B=0X05;
PORTA=0x00;
    while(1)
    {TCNT1H=0Xfa;
TCNT1L=0X00;
while((TIFR&0x04)==0);
PORTA=PORTA^0xff;
TIFR|=0x04;
       
    }
}

TIMER/COUNTER1 of ATMEGA32

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register
(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 89. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter
value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B).The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output compare interrupt request.The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins. The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be usedas an alternative, freeing the OCR1A to be used as PWM output.

Generate a 1s delay using TIMER0 in ATMEGA32

#include <avr/io.h>
void delay();
int main(void)
{  
 DDRB=0xff;
    DDRA=0XFF;
PORTA=0XFF;
TCCR0=0X05;
 

  while(1)
    {
      delay();
 PORTA=PORTA^0xff; 

    }
}
void delay()
{int i;
for(i=0;i<7;i++)
    {    TCNT0=0Xf0;  
     
     while((TIFR&0x01)==0);
 TIFR|=0x01;
 }
}

TIMER/COUNTER0 MODULE OF ATMEGA32L

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The
main features are:
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC0).The compare match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request.